/*-----------------------------------------------------------*/
/* Matthias Boesl                                            */
/* 2011-10-23                                                */
/* lpc clock initialization                                  */
/*-----------------------------------------------------------*/

#define OSCILLATOR_FQ            12000000
#define MAIN_FREQUENCY           ((OSCILLATOR_FQ * 2 * PLL_MULTIPLIER) / PLL_DIVIDER) / CLK_DIVIDER

/* PLL source selection */
#define CLOCK_SOURCE_INTERNAL    0x00
#define CLOCK_SOURCE_EXTERNAL    0x01
#define CLOCK_SOURCE_RTC         0x10

#define PLL_ENABLED              (1 << 0)
#define PLL_CONNECT              (1 << 1)
#define PLL_DISABLED             0x00

#define PLL_MULTIPLIER           16
#define PLL_DIVIDER              1
#define CLK_DIVIDER              4

#define PLL_M_VALUE              (PLL_MULTIPLIER - 1)
#define PLL_N_VALUE              ((PLL_DIVIDER - 1) << 16)
#define CLK_DIVIDER_VALUE        (CLK_DIVIDER -1)

#define PLL1_M                   3
#define PLL1_P                   1
#define PLL1_CFG_VALUE           ((PLL1_M)|(PLL1_P << 5))

#define OSC_ENABLE               (1 << 5)
#define OSC_READY                (1 << 6)

#define PLL0_STAT                (1 << 25)
#define PLL0_LOCKED              (1 << 26)

#define PLL1_STAT                (1 << 9)
#define PLL1_LOCKED              (1 << 10)

/* Flash timing for 100 MHz */
#define FLASH_TIMING_VALUE       ((0x04 << 12)|0x03A)

#define CCLK_QUARTER             0x00
#define CCLK_NO_DIVIDE           0x01
#define CCLK_HALF                0x02
#define CCLK_EIGHT               0x03

/* Peripheral clock selection 1 */
#define PCLK_WDT_DIVIDER                 1
#define PCLK_TIMER0_DIVIDER              1
#define PCLK_TIMER1_DIVIDER              1
#define PCLK_UART0_DIVIDER               1
#define PCLK_UART1_DIVIDER               1
#define PCLK_PWM1_DIVIDER                1
#define PCLK_I2C0_DIVIDER                1
#define PCLK_SPI_DIVIDER                 1
#define PCLK_SSP1_DIVIDER                1
#define PCLK_DAC_DIVIDER                 1
#define PCLK_ADC_DIVIDER                 4
#define PCLK_CAN1_DIVIDER                1
#define PCLK_CAN2_DIVIDER                1
#define PCLK_ACF_DIVIDER                 1

/* Peripheral clock selection 2 */
#define PCLK_QEI_DIVIDER                 1
#define PCLK_GPIOINT_DIVIDER             1
#define PCLK_PCB_DIVIDER                 1
#define PCLK_I2C1_DIVIDER                1
#define PCLK_SSP0_DIVIDER                1
#define PCLK_TIMER2_DIVIDER              1
#define PCLK_TIMER3_DIVIDER              1
#define PCLK_UART2_DIVIDER               1
#define PCLK_UART3_DIVIDER               1
#define PCLK_I2C2_DIVIDER                1
#define PCLK_I2S_DIVIDER                 1
#define PCLK_RIT_DIVIDER                 1
#define PCLK_SYSCON_DIVIDER              1
#define PCLK_MC_DIVIDER                  1

/* get divider bit value from divider */
#define GET_DIVIDER(divider) ((divider == 1) ? (CCLK_NO_DIVIDE) :((divider == 2) ? (CCLK_HALF) :((divider == 4) ? (CCLK_QUARTER) :(CCLK_EIGHT))))


/* Peripheral clock selection 1 */
#define PCLK_WDT                 (GET_DIVIDER(PCLK_WDT_DIVIDER) << 0)
#define PCLK_TIMER0              (GET_DIVIDER(PCLK_TIMER0_DIVIDER) << 2)
#define PCLK_TIMER1              (GET_DIVIDER(PCLK_TIMER1_DIVIDER) << 4)
#define PCLK_UART0               (GET_DIVIDER(PCLK_UART0_DIVIDER) << 6)
#define PCLK_UART1               (GET_DIVIDER(PCLK_UART1_DIVIDER) << 8)
#define PCLK_PWM1                (GET_DIVIDER(PCLK_PWM1_DIVIDER) << 12)
#define PCLK_I2C0                (GET_DIVIDER(PCLK_I2C0_DIVIDER) << 14)
#define PCLK_SPI                 (GET_DIVIDER(PCLK_SPI_DIVIDER) << 16)
#define PCLK_SSP1                (GET_DIVIDER(PCLK_SSP1_DIVIDER) << 20)
#define PCLK_DAC                 (GET_DIVIDER(PCLK_DAC_DIVIDER) << 22)
#define PCLK_ADC                 (GET_DIVIDER(PCLK_ADC_DIVIDER) << 24)
#define PCLK_CAN1                (GET_DIVIDER(PCLK_CAN1_DIVIDER) << 26)
#define PCLK_CAN2                (GET_DIVIDER(PCLK_CAN2_DIVIDER) << 28)
#define PCLK_ACF                 (GET_DIVIDER(PCLK_ACF_DIVIDER) << 30)

/* Peripheral clock selection 2 */
#define PCLK_QEI                 (GET_DIVIDER(PCLK_QEI_DIVIDER) << 0)
#define PCLK_GPIOINT             (GET_DIVIDER(PCLK_GPIOINT_DIVIDER) << 2)
#define PCLK_PCB                 (GET_DIVIDER(PCLK_PCB_DIVIDER) << 4)
#define PCLK_I2C1                (GET_DIVIDER(PCLK_I2C1_DIVIDER) << 6)
#define PCLK_SSP0                (GET_DIVIDER(PCLK_SSP0_DIVIDER) << 10)
#define PCLK_TIMER2              (GET_DIVIDER(PCLK_TIMER2_DIVIDER) << 12)
#define PCLK_TIMER3              (GET_DIVIDER(PCLK_TIMER3_DIVIDER) << 14)
#define PCLK_UART2               (GET_DIVIDER(PCLK_UART2_DIVIDER) << 16)
#define PCLK_UART3               (GET_DIVIDER(PCLK_UART3_DIVIDER) << 18)
#define PCLK_I2C2                (GET_DIVIDER(PCLK_I2C2_DIVIDER) << 20)
#define PCLK_I2S                 (GET_DIVIDER(PCLK_I2S_DIVIDER) << 22)
#define PCLK_RIT                 (GET_DIVIDER(PCLK_RIT_DIVIDER) << 26)
#define PCLK_SYSCON              (GET_DIVIDER(PCLK_SYSCON_DIVIDER) << 28)
#define PCLK_MC                  (GET_DIVIDER(PCLK_MC_DIVIDER) << 30)




#define PCLK1_VALUE              (PCLK_WDT | PCLK_TIMER0 | PCLK_TIMER1 | PCLK_UART0 | PCLK_UART1 | PCLK_PWM1 | PCLK_I2C0 | \
                                  PCLK_SPI | PCLK_SSP1 | PCLK_DAC | PCLK_ADC | PCLK_CAN1 | PCLK_CAN2 | PCLK_ACF)
#define PCLK2_VALUE              (PCLK_QEI | PCLK_GPIOINT | PCLK_PCB | PCLK_I2C1 | PCLK_SSP0 | PCLK_TIMER2 | PCLK_TIMER3 | \
                                  PCLK_UART2 | PCLK_UART3 | PCLK_I2C2 | PCLK_I2S | PCLK_RIT | PCLK_SYSCON | PCLK_MC)



void clock_init(void);

